With broadening use of portable electronic products, semiconductor devices require increasingly miniaturization and large capacity. To achieve the miniaturization and the large capacity, a large number of semiconductor chips need to be mounted in a semiconductor package and the semiconductor package need to be light, thin and compact. In an effort to achieve the above structure, an embedded package has been suggested in the art, in which a chip is embedded in a board instead of being arranged on the surface of a board.
FIG. 1 is a cross-sectional view illustrating a known embedded package.
Referring to FIG. 1, a bump 2 is formed on a bonding pad 1A of a semiconductor chip 1. The semiconductor chip 1 is attached to a core layer 3 in a face-up type by the medium of an adhesive component 8, and an insulation component 4 is laminated on the semiconductor chip 1 and the core layer 3. Then, the insulation component 4 is etched to be planarized such that the bump 2 is exposed. After forming a circuit wiring line 5 on the bump 2 and the insulation component 4 to be electrically connected to the bump 2, a solder resist pattern 6 is formed on the insulation component 4 and the circuit wiring line 5 to expose a portion of the circuit wiring line 5, and a solder ball 7 is mounted to the exposed portion of the circuit wiring line 5.
The embedded package configured as mentioned above provides an advantage in terms of high speed operation due to the fact that the transfer length of an electrical signal between the semiconductor chip 1 and an external connection terminal such as the solder ball 7 is shortened. However, because a distance H between an active region of the semiconductor chip 1 and the circuit wiring line 5 is short, parasitic capacitance induced between the integrated circuit of the semiconductor chip 1 and the circuit wiring line 5 becomes large, and it is difficult to achieve high speed operation in spite of the shortened transfer length of an electrical signal.
While the distance H between the semiconductor chip 1 and the circuit wiring line 5 may be lengthened by increasing the height of the bump 2, if the height of the bump 2 increases, adjacent bumps 2 may be short-circuited.